As semiconductor technologies evolve, integrated circuits (IC) have migrated to small feature sizes, such as 65 nanometers, 45 nanometers, 32 nanometers and below. Semiconductor technologies with small feature sizes lead to more interactions between semiconductor fabrication and design. For example, the impact of parasitic effects will become more important for devices with small feature sizes. A variety of simulation and optimization procedures may be performed by IC designers to ensure the devices with small feature sizes meet the performance index to which they are specified.
Semiconductor resistors are widely used in integrated circuits. Semiconductor resistors may be formed by doping an active region of the substrate of an integrated circuit. Alternatively, semiconductor resistors may be formed by depositing a plurality of polysilicon layers formed over the substrate. A semiconductor resistor may be formed by a plurality of resistor components connected in series or parallel. For example, the resistor components of a semiconductor resistor may be doped active regions formed in the substrate. A variety of interconnect structures connect the resistor components together to form the semiconductor resistor.
Semiconductor resistors may be employed to form critical control circuits of integrated circuits. For example, in a band gap reference circuit, the reference voltage is determined by a ratio of two semiconductor resistors coupled to the band gap reference circuit. As such, the ratio of these two semiconductor resistors is critical for maintaining accurate operations so that the band gap reference circuit may be able to generate an accurate reference voltage.
The layout of semiconductor resistors may cause a plurality of resistance variations due to parasitic parameters contributed by interconnects, which are used to couple different resistor components. Such variations may cause a shift of the ratio between two semiconductor resistors. As such, some critical performance indexes such as timing, noise and reliability may be negatively affected.
Various Electronic Design Automation (EDA) tools may be used to extract parasitic capacitance, inductance and resistance. For example, EDA tools such as Star-RCXT from SYNOPSYS, CALIBRE from Mentor Graphics and/or the like may first receive a SPICE model file from an IC foundry and extract parasitic parameters subsequently.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.